In recent years computer users have demanded ever increasing amounts of information to be displayed in a graphical form. Displaying information in graphical form requires very large amounts of memory to store the graphics data that produces a graphical display. Recently many developers have created three-dimensional graphical display applications that further multiply the amount of data needed to create a graphical display.
A portion of a typical computer system that implements graphical display applications is shown in FIG. 1. The computer system 10 includes a processor 12 coupled by a processor bus 14 to a system controller 16. The computer system 10 also includes a system memory 18 coupled by a memory bus 20 to the system controller 16. The computer system 10 also includes a graphics controller 22 coupled by a Peripheral Component Interconnect (PCI) bus 24 to the system controller 16. The graphics controller 22 controls how graphics images are displayed on a graphics monitor 26 coupled to the graphics controller. Also coupled to the graphics controller 22 is a local frame buffer 28 that stores graphics information that is used to display the graphics images on the graphics monitor 26.
Typically, a portion of the graphics data used to produce graphical displays is stored in the local frame buffer 28 while another portion of the graphics data is stored in the system memory 18. The speed at which the graphics controller 22 can display graphics on the graphics monitor 26 is limited by the speed at which the graphics controller 22 can receive the graphics data from the system memory 18. The speed at which the graphics controller 22 can retrieve the graphics data from the system memory 18 is limited by the speed of the PCI bus 24.
A relatively new bus, known as an Accelerated graphics Port (AGP), for connecting graphics controllers, such as the graphics controller 22, to system controllers, such as the system controller 16, has been developed by Intel Corporation to replace PCI buses for graphics applications. The preferred AGP bus provides the graphics controller 22 with a continuous view of the address space for the graphics data in the system memory 18. However, because the system controller 16 typically dynamically allocates the system memory 18 in random 4-kilobyte pages, it is necessary to provide an address mapping mechanism that maps the random 4-kilobyte pages into a single, contiguous address space. According to the specification published by Intel on Jul. 31, 1996 for the AGP bus, the address remapping is accomplished via a table called the graphics address remapping table (GART).
The Intel AGP specification suggests that the GART be implemented in a system controller, such as the system controller 16. However, implementing the GART in the system controller 16 likely would require a very large number of programmable registers. Such programmable registers would require many transistors, and thus, likely would be prohibitively expensive to manufacture.